RISC-V Supreme
Massively parallel RISC-V at data-center scale — many small cores presented as one coherent operating story.
Many cores
Small RISC-V cores in parallel
One story
A coherent operating model
Data-center
The scale it targets
Parallelism is easy to buy, hard to operate.
Filling a data center with small, efficient RISC-V cores is now a purchasing decision. Operating thousands of them as one system is not — scheduling, memory, failure and observability were designed around a smaller number of larger machines.
Without a coherent operating story, massive parallelism turns into massive operational surface. The cores are cheap; the coordination is where the cost moves.
Make the fleet legible.
01
Many small cores
The design assumes a large population of small RISC-V cores as the substrate, rather than a handful of large processors — betting on parallel efficiency at data-center scale.
02
One coherent operating model
On top of that substrate sits a single operating story for scheduling, memory and failure, so the fleet is administered as one system instead of thousands of independent machines.
Research, stated plainly.
| Milestone | Status | Evidence |
|---|---|---|
| Operating-model design | In progress | Internal study |
| Small-scale cluster | Next | — |
| Scheduling & failure model | Next | — |
| Data-center pilot | Next | — |
Figures on this page are targets and internal measurements at proof-of-concept stage. We share the methodology with anyone who wants to run it.
A cluster to argue against.
The near-term goal is a small cluster that makes the operating model concrete — enough cores to expose the scheduling, memory and failure questions the design has to answer.
RISC-V Supreme spins out of Research ByIQ if the operating model holds as the core count grows.